R. R. Logic Systems

About

The team of compiler professionals at R. R. Logic Systems were together as an entity under the umbrella of various organizations for over four years before launching RRLogic in 2011.  The team comprises of four senior experts in the area of compilers each with over 16 years of experience in the the field, having worked with various MNCs in different capacities.  Each of them is a hands-on developer.

Besides there is a group of junior professionals with experience ranging from 2 to 8 years in the field of compilers and tools.  The team has grown organically over the years with fresh talent being selected almost every year and trained in the relevant skills.  There is a cumulative experience of more than 150 man years within the company.

The company believes in identifying and grooming fresh talent, and creating an environment of trust for them to grow on their own, since it is very difficult to readily find such talent in the industry.  So far the company has been successful in the efforts.  Our Alumni have also gone out to explore opportunities in MNCs and have been doing very well there.  We are proud of them and of our contribution to the industry in grooming talent in this specialized area.

The Management Team

Ayonam has been in the industry for over 29 years working in the area of Compilers and Tools.  He started his career with a start up Synergy Infotech Private Limited where he learned the ropes of Compilers.  He then moved on to Hewlett Packard, India Software Operations, where he worked on the Dynamic Binary Translator, ARIES and the Dynamic Profiling Tool, Caliper for the Itanium platform.  After a stint of over 7 years at HP, he moved on to work with 4 different start ups before deciding to venture out on his own, which culminated in the formation of R. R. Logic Systems.  Ayonam has been an avid engineer and during the later parts of his career has also been managing teams of Compiler professionals with complete delivery responsibility.  Ayonam holds a Bachelors degree in Electrical Engineering from Govt. College of Engineering, Karad, India and a Masters degree in High Voltage Engineering from the Indian Institute of Science, Bangalore, India.

Rajesh has been working on Compilers for HPC and AI since 2010.  He has worked extensively on heterogenous architectures for HPC.  More recently, he has been working on Graph Compilers for AI Inferencing for Convolutional Networks, Recurrent Networks, LLMs and Mamba.  He has held senior positions at Math Works and was a Vice President at Goldman Sachs.  Rajesh holds a Ph.D. in Compilers from the Indian Institute of Science, Bangalore, India.

Kaustav Guha is a seasoned Electronic Design Automation (EDA) professional with nearly two decades of industry experience spanning simulation and verification, static timing analysis, low power design, and high-performance EDA tool development.  He holds an MS in Electronics and Communication from IIT Madras and a B.E. from the University of Madras.

Before joining R. R. Logic Systems, Kaustav served as Principal Engineer at Siemens EDA (Siemens Digital Industries Software) for close to nine years, where he led work on elaboration, optimization, and simulation in Questa, advanced SystemVerilog and VHDL language feature support, and performance and memory optimization of large-scale EDA tools.  Prior to that, he was Principal Software Engineer at Cadence Design Systems, working on Static Timing Analysis, Mixed Signal Flows, and Distributed Processing.

Kaustav is the inventor on four granted US patents in EDA and the author of six peer-reviewed publications at venues including DAC and DVCon.  His technical expertise spans digital design simulation, formal verification, signoff DRC, computer architecture, and performance-centric software development, with hands-on proficiency in C/C++, Python, SystemVerilog, VHDL, UPF, and Verilog.

At R. R. Logic Systems, he leads the development of Hydra — a Verilog simulation and visualization environment built as a VS Code extension — aimed at making hardware description language development more transparent and accessible for engineers and students alike.

About

The team of compiler professionals at R. R. Logic Systems have been together as an entity under the umbrella of various organizations for over four years.  The team comprises of four senior experts in the area of compilers each with over 16 years of experience in the the field, having worked with various MNCs in different capacities.  Each of them is a hands-on developer.

Besides there is a group of junior professionals with experience ranging from 2 to 8 years in the field of compilers and tools.  The team has grown organically over the years with fresh talent being selected almost every year and trained in the relevant skills.  There is a cumulative experience of more than 70 man years within the company.

The company believes in identifying and grooming fresh talent, and creating an environment of trust for them to grow on their own, since it is very difficult to readily find such talent in the industry.  So far the company has been successful in the efforts.  Our Alumni have also gone out to explore opportunities in MNCs and have been doing very well there.  We are proud of them and of our contribution to the industry in grooming talent in this specialized area.

The Management Team

Ayonam has been in the industry for over 29 years working in the area of Compilers and Tools.  He started his career with a start up Synergy Infotech Private Limited where he learned the ropes of Compilers.  He then moved on to Hewlett Packard, India Software Operations, where he worked on the Dynamic Binary Translator, ARIES and the Dynamic Profiling Tool, Caliper for the Itanium platform.  After a stint of over 7 years at HP, he moved on to work with 4 different start ups before deciding to venture out on his own which culminated in the formation of R. R. Logic Systems.  Ayonam has been an avid engineer and during the later parts of his career has also been managing teams of Compiler professionals with complete delivery responsibility.  Ayonam holds a Bachelors degree in Electrical Engineering from Govt. College of Engineering, Karad, India and a Masters degree in High Voltage Engineering from the Indian Institute of Science, Bangalore, India.

Rajesh Thakur, Chief Technical Architect

Rajesh has been working on Compilers for HPC and AI since 2010.  He has worked extensively on heterogenous architectures for HPC.  More recently, he has been working on Graph Compilers for AI Inferencing for Convolutional Networks, Recurrent Networks, LLMs and Mamba.  He has held senior positions at Math Works and was a Vice President at Goldman Sachs.  Rajesh holds a Ph.D. in Compilers from the Indian Institute of Science, Bangalore, India.

Kaustav Guha is a seasoned Electronic Design Automation (EDA) professional with nearly two decades of industry experience spanning simulation and verification, static timing analysis, low power design, and high-performance EDA tool development.  He holds an MS in Electronics and Communication from IIT Madras and a B.E. from the University of Madras.

Before joining R. R. Logic Systems, Kaustav served as Principal Engineer at Siemens EDA (Siemens Digital Industries Software) for close to nine years, where he led work on elaboration, optimization, and simulation in Questa, advanced SystemVerilog and VHDL language feature support, and performance and memory optimization of large-scale EDA tools.  Prior to that, he was Principal Software Engineer at Cadence Design Systems, working on Static Timing Analysis, Mixed Signal Flows, and Distributed Processing.

Kaustav is the inventor on four granted US patents in EDA and the author of six peer-reviewed publications at venues including DAC and DVCon.  His technical expertise spans digital design simulation, formal verification, signoff DRC, computer architecture, and performance-centric software development, with hands-on proficiency in C/C++, Python, SystemVerilog, VHDL, UPF, and Verilog.

At R. R. Logic Systems, he leads the development of Hydra — a Verilog simulation and visualization environment built as a VS Code extension — aimed at making hardware description language development more transparent and accessible for engineers and students alike.